(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to integrate the fabrication of logic devices, and dynamic random access memory, (DRAM), devices, on the same semiconductor chip.
(2) Description of Prior Art
The semiconductor industry is continually striving to increase device, as well as chip performance. The ability to form logic devices, and memory devices, such as embedded DRAM devices, on the same semiconductor chip, via novel process integration procedures, has resulted in a decrease in performance degrading resistances, when compared to counterparts in which additional metal wiring, accomplished during packaging procedures, is needed to connect the logic chips to the memory chips. This invention will describe a novel fabrication process, allowing integration of high performance logic devices, and embedded DRAM devices, on the same semiconductor chip, however this invention will feature the integration of process sequences, needed to obtain superior logic devices, without degrading of the DRAM devices. For example Self-ALigned metal silICIDE, (SALICIDE), regions are formed for the gate as well as for the source/drain regions of the logic devices,, while only forming SALICIDE on the DRAM gate structures. This combination, obtained as a result of the process sequence described in this invention, results in a reduction in DRAM junction leakage, when compared to DRAM counterparts, fabricated using a salicide region on the source/drain area. In addition the integration process described in this invention also results in a reduction in processing costs, as a result of: doping of the DRAM polysilicon gate structure, without additional photolithographic masking procedures; creation of the DRAM lightly doped source/drain regions, without additional photolithographic masking; and the simultaneous saliciding of both the logic, and DRAM gate structures. Prior art, such as Yoo et al, in U.S. Pat. No. 5,866,451, as well as Liang, in U.S. Pat. No. 5,702,988, describe processes in which both logic and memory devices are formed on the same semiconductor chip, however those prior arts do not describe the novel sequence of process steps, used in the present invention, which offer yield enhancements, (non-salicided DRAM source/drain), as well as cost reductions, in terms of reductions in photolithographic masking procedures, resulting form the sharing of specific process steps.